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MPE603E7VEC/D (Motorola Order Number) 9/97
TM
Advance Information
PID7v-EC603e Hardware Specifications
The EC603e is implemented in both a 2.5-volt version (PID 0007v EC603e microprocessor, abbreviated as PID7v-EC603e) and a 3.3-volt version (PID 0006 EC603e microprocessor, abbreviated as PID6-EC603e). This document describes the pertinent physical characteristics of the PID7v-EC603e. For functional characteristics of the processor, refer to the MPC603e/EC603e RISC Microprocessor User's Manual. The PID7v-EC603e microprocessor from Motorola is an implementation of the PowerPC(R) family of reduced instruction set computing (RISC) microprocessors. The EC603e microprocessor for embedded systems is functionally equivalent to the MPC603e with the exception of the floating-point unit which is not supported on the EC603e. This document contains the following topics:
Topic Page
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EC603e Embedded RISC Microprocessor Family:
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Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.5, "Pin Assignments" Section 1.6, "Pinout Listings" Section 1.7, "Package Descriptions" Section 1.8, "System Design Information" Section 1.9, "Ordering Information" Appendix A, "General Handling Recommendations for the C4-CQFP"
2 3 4 4 15 17 21 25 31 32
The PowerPC name is a registered trademark and the PowerPC logotype and PowerPC 603 are trademarks of International Busines Machines Corporation, used by Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK. This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola Inc., 1997. All rights reserved.
PID7v-EC603e Hardware Specifications
To locate any published errata or updates for this document, refer to the website at http://www.mot.com/ SPS/PowerPC/.
1.1 Overview
This section describes the features of the PID7v-EC603e and describes briefly how those units interact. The PID7v-EC603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set computing (RISC) microprocessors. The PID7v-EC603e implements the 32-bit portion of the PowerPC architecture specification, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. The PID7v-EC603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power consumed by the processor. The fourth is a dynamic power management mode that causes the functional units in the PID7vEC603e to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. The PID7v-EC603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the PID7v-EC603e makes completion appear sequential. The PID7v-EC603e integrates four execution units--an integer unit (IU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for PID7v-EC603e-based systems. Most integer instructions execute in one clock cycle. The PID7v-EC603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The PID7v-EC603e also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority. The PID7v-EC603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The PID7v-EC603e interface protocol allows multiple masters to compete for system resources through a central external arbiter. The PID7v-EC603e provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol is a compatible subset of the MESI (modified/exclusive/shared/ invalid) four-state protocol and operates coherently in systems that contain four-state caches. The PID7vEC603e supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/O. The PID7v-EC603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface compatibility with TTL devices.
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PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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1.2 Features
This section summarizes features of the PID7v-EC603e's implementation of the PowerPC architecture. Major features of the PID7v-EC603e are as follows: * High-performance, superscalar microprocessor -- As many as three instructions issued and retired per clock -- As many as five instructions in execution per clock -- Single-cycle execution for most instructions * Four independent execution units and one register file -- BPU featuring static branch prediction -- A 32-bit IU
-- LSU for data transfer between data cache and GPRs
-- SRU that executes condition register (CR), special-purpose register (SPR) instructions, and integer add/compare instructions -- Thirty-two GPRs for integer operands * High instruction and data throughput
-- Programmable static branch prediction on unresolved conditional branches -- A six-entry instruction queue that provides lookahead capability -- Independent pipelines with feed-forwarding that reduces data dependencies in hardware -- 16-Kbyte data cache--four-way set-associative, physically addressed; LRU replacement algorithm -- 16-Kbyte instruction cache--four-way set-associative, physically addressed; LRU replacement algorithm -- Cache write-back or write-through operation programmable on a per page or per block basis -- BPU that performs CR lookahead operations -- Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size -- A 64-entry, two-way set-associative ITLB -- A 64-entry, two-way set-associative DTLB -- Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks -- Software table search operations and updates supported through fast trap mechanism -- 52-bit virtual address; 32-bit physical address * Facilities for enhanced system performance -- A 32- or 64-bit split-transaction external data bus with burst transfers -- Support for one-level address pipelining and out-of-order bus transactions
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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-- Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
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-- Zero-cycle branch capability (branch folding)
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*
Integrated power management -- Low-power 2.5/3.3-volt design -- Internal processor/bus clock multiplier that provides 2/1, 2.5/1, 3/1, 3.5/1, 4/1, 4.5/1, 5/1, 5.5/1, and 6/1 ratios -- Three power saving modes: doze, nap, and sleep -- Automatic dynamic power reduction when internal functional units are idle
*
In-system testability and debugging features through JTAG boundary-scan capability
The following list provides a summary of the general parameters of the PID7v-EC603e: Technology Die size Transistor count Logic design Package Core power supply I/O power supply 0.35 m CMOS, five-layer metal 10.5 mm x 7.5 mm (79 mm2) 2.6 million Fully-static
Surface mount 240-pin ceramic quad flat pack (CQFP) or 255 ceramic ball grid array (CBGA)
This section provides the AC and DC electrical specifications and thermal characteristics for the PID7vEC603e.
1.4.1 DC Electrical Characteristics
The tables in this section describe the PID7v-EC603e DC electrical characteristics. Table 1 provides the absolute maximum ratings.
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1.4 Electrical and Thermal Characteristics
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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2.5 5% V dc 3.3 5% V dc
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1.3 General Parameters
Table 1. Absolute Maximum Ratings
Characteristic Core supply voltage PLL supply voltage I/O supply voltage Input voltage Storage temperature range Notes: Vdd AVdd OVdd Vin Tstg Symbol Value -0.3 to 2.75 -0.3 to 2.75 -0.3 to 3.6 -0.3 to 5.5 -55 to 150 Unit V V V V C
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Vin must not exceed OVdd by more than 2.5 V at any time, including during power-on reset. 3. Caution: OVdd must not exceed Vdd/AVdd by more than 1.2 V at any time, including during power-on reset.
Table 2 provides the recommended operating conditions for the PID7v-EC603e.
Table 2. Recommended Operating Conditions
Characteristic Core supply voltage PLL supply voltage I/O supply voltage Input voltage Symbol Vdd AVdd OVdd Vin Tj Value 2.375 to 2.625 2.375 to 2.625 3.135 to 3.465 GND to 5.5 0 to 105 Unit V V V V C
Junction temperature
Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 3 provides the package thermal characteristics for the PID7v-EC603e.
Table 3. Thermal Characteristics
Characteristic Motorola wire-bond CQFP package thermal resistance, junction-to-case (typical) CBGA package thermal resistance, junction-to-top-of-die Symbol JC JC Value 2.2 0.03 Rating C/W C/W
Note: Refer to Section 1.8, "System Design Information," for more details about thermal management.
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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4. Caution: Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time, including during power-on reset.
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Table 4 provides the DC electrical characteristics for the PID7v-EC603e.
Table 4. DC Electrical Specifications
Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C
Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = 3.465 V Vin = 5.5 V Hi-Z (off-state) leakage current, Vin = 3.465 V Vin = 5.5 V Output high voltage, IOH = -7 mA Output low voltage, IOL = 7 mA
Symbol VIH VIL CVIH CVIL
Min 2.0 GND 2.4 GND --
Max 5.5 0.8 5.5 0.4 30 300
Unit V V V V A A A A V V pF
Notes
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Iin Iin -- ITSI -- ITSI -- VOH VOL Cin Cin 2.4 -- -- --
1,2 1,2 1,2 1,2
30 300
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--
0.4 10.0
Capacitance, Vin = 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY) Notes:
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Capacitance, Vin = 0 V, f = 1 MHz (excludes TS, ABB, DBB, and ARTRY)
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15.0
pF
3
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals). 2. The leakage is measured for nominal OVdd and Vdd or both OVdd and Vdd must vary in the same direction (for example, both OVdd and Vdd vary by either +5% or -5%). 3. Capacitance is periodically sampled rather than 100% tested.
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PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Table 5 provides the power consumption for the PID7v-EC603e.
Table 5. Power Consumption
Processor (CPU) Frequency Unit 166 MHz Full-On Mode (DPM Enabled) Typical Max. Doze Mode Typical Nap Mode Typical Sleep Mode Typical Sleep Mode--PLL Disabled Typical 60 70 80 1.2 3.0 4.0 4.0 W W 200 MHz
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1.5 120
5.0
W
mW
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100
mW
Sleep Mode--PLL and SYSCLK Disabled Maximum Notes: 60
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60
mW
60
mW
1.These values apply for all valid PLL_CFG[0-3] settings and do not include output driver power (OVdd) or analog supply power (AVdd). OVdd power is system dependent but is typically 10% of Vdd. Worst-case AVdd = 15 mW. 2. Typical power is an average value measured at Vdd = AVdd = 2.5 V, OVdd = 3.3V, in a system executing typical applications and benchmark sequences. 3. Maximum power is measured at 2.625 V using a worst-case instruction mix.
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the PID7v-EC603e. These specifications are for 166 and 200 MHz processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0-3] signals. All timings are specified respective to the rising edge of SYSCLK. PLL_CFG signals should be set prior to power up and not altered afterwards.
1.4.2.1 Clock AC Specifications
Table 6 provides the clock AC timing specifications as defined in Figure 1. After fabrication, parts are sorted by maxium processor core frequency as shown in Section 1.4.2.1, "Clock AC Specifications" and tested for conformance to the AC specifications for that frequency. Parts are sold by maximum processor core frequency; see Section 1.9, "Ordering Information."
Table 6. Clock AC Timing Specifications
Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C
Num
Characteristic
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166 MHz 200 MHz Max Min Max 167 333 66.67 40.0 2.0 60.0 150 100 125 250 25 15 -- 40.0 -- -- 200 400 66.67 40.0 2.0 60.0 150 100
Unit
Notes
Min Processor frequency VCO frequency SYSCLK frequency 1 2,3 4 SYSCLK cycle time 125 250 25
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MHz MHz MHz ns ns % ps s
1 1 1
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15 -- 40.0 -- --
SYSCLK rise and fall time
2 3 4 3,5
SYSCLK duty cycle measured at 1.4 V SYSCLK jitter
PID7v-EC603e internal PLL-relock time Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in Section 1.8, "System Design Information," for valid PLL_CFG[0-3] settings. 2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. 3. Timing is guaranteed by design and characterization, and is not tested. 4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term combined) must be under 150 ps. 5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100 s) during the power-on reset sequence.
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Figure 1 provides the SYSCLK input timing diagram.
1 4 4 CVih VM VM VM CVil 2 3
SYSCLK
VM = Midpoint Voltage (1.4 V)
Figure 1. SYSCLK Input Timing Diagram
1.4.2.2 Input AC Specifications
Table 7 provides the input AC timing specifications for the PID7v-EC603e as defined in Figure 2 and Figure 3.
Table 7. Input AC Timing Specifications1
Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C
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Num
Characteristic
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Min 2.5 4.0 8 1.0 1.0 0
166 and 200 MHz Unit Max -- ns 2 Notes
10a
Address/data/transfer attribute inputs valid to SYSCLK (input setup)
10c
Mode select inputs valid to HRESET (input setup) (for DRTRY, QACK and TLBISYNC) SYSCLK to address/data/transfer attribute inputs invalid (input hold) SYSCLK to all other inputs invalid (input hold) HRESET to mode select inputs invalid (input hold) (for DRTRY, QACK, and TLBISYNC)
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10b
All other inputs valid to SYSCLK (input setup)
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-- --
ns tsysclk ns
3 4,5, 6,7 2
11a
--
11b 11c
-- --
ns ns
3 4,6,7
Notes:
1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin. 2. Address/data/transfer attribute input signals are composed of the following--A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[0-7]. 3. All other input signals are composed of the following--TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3). 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. These values are guaranteed by design, and are not tested. 7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Figure 2 provides the input timing diagram for the PID7v-EC603e.
SYSCLK
10a 10b
VM 11a 11b
ALL INPUTS
VM = Midpoint Voltage (1.4 V)
Figure 2. Input Timing Diagram
Figure 3 provides the mode select input timing diagram for the PID7v-EC603e.
HRESET
10c
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MODE PINS
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VM = Midpoint Voltage (1.4 V)
Figure 3. Mode Select Input Timing Diagram
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VM 11c
1.4.2.3 Output AC Specifications
Table 8 provides the output AC timing specifications for the PID7v-EC603e as defined in Figure 4.
Table 8. Output AC Timing Specifications1
Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5%, GND = 0 V dc, 0 Tj 105 C, CL = 50 pF (unless otherwise noted)
166 and 200 MHz Num Characteristic Min 12 13a 13b 14a SYSCLK to output driven (output enable time) SYSCLK to output valid (5.5 V to 0.8 V--TS, ABB, ARTRY, DBB) SYSCLK to output valid (TS, ABB, ARTRY, DBB) 1.0 Max -- 9.0 8.0 11.0 ns ns ns ns 3 5 3 Unit Notes
SYSCLK to output valid (5.5 V to 0.8 V--all except TS, ABB, ARTRY, DBB) SYSCLK to output valid (all except TS, ABB, ARTRY, DBB) SYSCLK to output invalid (output hold)
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-- -- -- -- 1.0 -- -- -- 0.2 * tsysclk + 1.0 -- --
14b 15 16 17 18 19
9.0 -- 8.5 1.0 8.0 --
ns ns ns tsysclk ns ns
5 2
SYSCLK to output high impedance (all except ARTRY, ABB, DBB) SYSCLK to ABB, DBB, high impedance after precharge SYSCLK to ARTRY high impedance before precharge SYSCLK to ARTRY precharge enable
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4,6
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2,4,7
20 21 Notes:
Maximum delay to ARTRY precharge SYSCLK to ARTRY high impedance after precharge
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1.0 2.0
tsysclk tsysclk
4,7 5,7
1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4). 2. This minimum parameter assumes CL = 0 pF. 3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels). 4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 5. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V. 6. Nominal precharge width for ABB and DBB is 0.5 tsysclk. 7. Nominal precharge width for ARTRY is 1.0 tsysclk.
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Figure 4 provides the output timing diagram for the PID7v-EC603e.
SYSCLK
VM 14 15 12 16
VM
VM
13
TS
ABB, DBB
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18
ARTRY
VM = Midpoint Voltage (1.4 V)
Figure 4. Output Timing Diagram
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13 15 16 17 21 20 19
ALL OUTPUTS (Except TS, ABB, DBB, ARTRY)
1.4.3 JTAG AC Timing Specifications
Table 9 provides the JTAG AC timing specifications as defined in Figure 5 through Figure 8.
Table 9. JTAG AC Timing Specifications
Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5%, GND = 0 V dc, 0 Tj 105 C, CL = 50 pF
Num
Characteristic TCK frequency of operation 0
Min
Max 16 -- --
Unit MHz ns ns
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13
TCK cycle time TCK clock pulse width measured at 1.4 V TCK rise and fall times
62.5 25
TRST setup time to TCK rising edge TRST assert time
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0 3 ns 13 -- ns 40 6 -- ns -- ns 27 -- ns 4 3 0 25 4 3 25 24 -- -- 24 15 ns ns ns ns ns ns
1 2 2 VM VM VM
1
Boundary scan input data setup time Boundary scan input data hold time TCK to output data valid
2 2 3 3
TCK to output high impedance TMS, TDI data setup time TMS, TDI data hold time
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Non-test signal input timing with respect to TCK. 3. Non-test signal output timing with respect to TCK.
Figure 5 provides the JTAG clock input timing diagram.
TCK
3 3
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TCK to TDO data valid TCK to TDO high impedance
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Figure 5. JTAG Clock Input Timing Diagram
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VM = Midpoint Voltage (1.4 V)
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Figure 6 provides the TRST timing diagram.
TCK
4 VM
TRST
5
Figure 7 provides the boundary-scan timing diagram.
TCK
VM
Data Inputs
Data Outputs
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VM 9 8 12 13 12
8
Data Outputs
Data Outputs
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Figure 7. Boundary-Scan Timing Diagram
Figure 8 provides the test access port timing diagram.
TCK
TDI, TMS
TDO
TDO
TDO
Figure 8. Test Access Port Timing Diagram
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PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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VM 7 6 Input Data Valid Output Data Valid Output Data Valid VM 10 11 Input Data Valid Output Data Valid Output Data Valid
Figure 6. TRST Timing Diagram
1.5 Pin Assignments
The following sections contain the pinout diagrams for the PID7v-EC603e. Note that the PID7v-EC603e is offered in both ceramic quad flat pack (CQFP) and ceramic ball grid array (CBGA) packages.
1.5.1 Pinout Diagram for the CQFP Package
Figure 9 contains the CQFP pin assignments for the PID7v-EC603e.
OVDD GND OGND CI WT QACK TBEN TLBISYNC RSRV AP0 AP1 OVDD OGND AP2 AP3 CSE0 TC0 TC1 OVDD CLK_OUT OGND BR APE DPE CKSTP_OUT CKSTP_IN HRESET PLL_CFG0 SYSCLK PLL_CFG1 PLL_CFG2 AVDD PLL_CFG3 VDD GND LSSD_MODE L1_TSTCLK L2 _TSTCLK TRST TCK TMS TDI TDO TSIZ0 TSIZ1 TSIZ2 OVDD OGND TBST TT0 TT1 SRESET INT SMI MCP TT2 TT3 OVDD GND OGND GBL A1 A3 VDD A5 A7 A9 OGND GND OVDD A11 A13 A15 VDD A17 A19 A21 OGND GND OVDD A23 A25 A27 VDD DBWO DBG BG AACK GND A29 QREQ ARTRY OGND VDD OVDD ABB A31 DP0 GND DP1 DP2 DP3 OGND VDD OVDD DP4 DP5 DP6 GND DP7 DL23 DL24 OGND OVDD DL25 DL26 DL27 DL28 VDD OGND
PR PR EL EL IM IM IN IN AA RY RY
TOP VIEW
Figure 9. Pinout Diagram for the CQFP Package
240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
OVDD DL29 DL30 DL31 GND DH31 DH30 DH29 OGND OVDD DH28 DH27 DH26 DH25 DH24 DH23 OGND DH22 OVDD DH21 DH20 DH19 DH18 DH17 DH16 OGND DH15 OVDD DH14 DH13 DH12 DH11 DH10 DH9 OGND OVDD DH8 DH7 DH6 DL22 DL21 DL20 OGND OVDD DL19 DL18 DL17 DH5 DH4 DH3 OGND OVDD DH2 DH1 DH0 GND DL16 DL15 DL14 OGND
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
1
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
TT4 A0 A2 VDD A4 A6 A8 OVDD GND OGND A10 A12 A14 VDD A16 A18 A20 OVDD GND OGND A22 A24 A26 VDD DRTRY TA TEA DBDIS GND A28 CSE1 TS OVDD VDD OGND DBB A30 DL0 GND DL1 DL2 DL3 OVDD VDD OGND DL4 DL5 DL6 GND DL7 DL8 DL9 OVDD OGND DL10 DL11 DL12 DL13 VDD OVDD
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1.5.2 Pinout Diagram for the CBGA Package
Figure 10 (in part A) shows the pinout of the CBGA package as viewed from the top surface. Part B
shows the side profile of the CBGA package to indicate the direction of the top surface view.
Part A
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 A B
D E F G H J K L M N P R T
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Part B
Substrate Assembly Encapsulant
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Not to Scale
View Die
Figure 10. Pinout of the CBGA Package as Viewed from the Top Surface
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PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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1.6 Pinout Listings
The following sections provide the pinout listings for the PID7v-EC603e CQFP and CBGA packages.
1.6.1 Pinout Listing for the CQFP Package
Table 10 provides the pinout listing for the PID7v-EC603e CQFP package.
Table 10. Pinout Listing for the 240-pin CQFP Package
Signal Name A[0-31] Pin Number 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, 37 28 36 231, 230, 227, 226 218 32 209 27 219 237 221 215 216 Active High I/O I/O
IN A RY
AACK ABB AP[0-3] APE ARTRY AVDD BG BR CI CLK_OUT CKSTP_IN CKSTP_OUT CSE[0-1]1 DBB DBDIS DBG DBWO DH[0-31]
Low Low High Low Low High Low Low Low -- Low Low High Low Low Low Low High
Input I/O I/O Output I/O Input Input Output Output Output Input Output Output I/O Input Input Input I/O
DL[0-31]
PR
225, 150 145 153 26 25 115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, 89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73, 72, 71, 68, 67, 66 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100, 51, 52, 55, 56, 57, 58, 62, 63, 64 38, 40, 41, 42, 46, 47, 48, 50 217 156
EL
IM
High
I/O
DP[0-7] DPE DRTRY
High Low Low
I/O Output Input
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Table 10. Pinout Listing for the 240-pin CQFP Package (Continued)
Signal Name GBL GND HRESET INT LSSD_MODE2 L1_TSTCLK2 L2_TSTCLK2 MCP OGND OVDD3 1 9, 19, 29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, 239 214 188 Pin Number Active Low Low Low Low I/O I/O Input Input Input Input Input Input Input Input
204 203 186
IN A RY
205
Low -- -- Low Low
8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238
PLL_CFG[0-3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TC[0-1] TCK TDI TDO TEA TLBISYNC TMS TRST
213, 211, 210, 208 235 31 232 187 189
IM
10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 240
High
Input
High Low Low Low Low Low -- Low High Low High -- High High Low Low High Low
Input Input Output Output Input Input Input Input Input I/O Output Input Input Output Input Input Input Input
18
PR
212 155 234 192 224, 223 201 199 198 154 233 200 202
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Table 10. Pinout Listing for the 240-pin CQFP Package (Continued)
Signal Name TSIZ[0-2] TS TT[0-4] VDD3 WT Notes: 197, 196, 195 149 191, 190, 185, 184, 180 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 Pin Number Active High Low High High Low I/O Output I/O I/O Input Output
1. There are two CSE signals in the PID7v-EC603e--CSE0 and CSE1. The XATS signal in the PowerPC 603TM microprocessor is replaced by the CSE1 signal in the PID7v-EC603e. 2. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 3. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
1.6.2 Pinout Listing for the CBGA Package
Table 11. Pinout Listing for the 255 CBGA Package
A[0-31]
C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, GO2, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01
EL
Signal Name
IM
Table 11 provides the pinout listing for the PID7v-EC603e CBGA package.
Pin Number
IN A RY
236
Active High
I/O I/O
PR
L02
AACK ABB AP[0-3] APE ARTRY AVDD BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT CSE[0-1] DBB DBG DBDIS
Low Low High Low Low -- Low Low Low Low Low -- High Low Low Low
Input I/O I/O Output I/O -- Input Output Output Input Output Output Output I/O Input Input
K04
C01, B04, B03, B02 A04 J04 A10 L01 B06 E01 D08 A06 D07 B01, B05 J14 N01 H15
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Table 11. Pinout Listing for the 255 CBGA Package (Continued)
Signal Name DBWO DH[0-31] G04 P14, T16, R15, T15, R13, R12, P11, N11, R11,T12, T11, R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04 M02, L03, N02, L04, R01, P02, M04, R02 A05 G16 F01 Pin Number Active Low High I/O Input I/O
DL[0-31]
High
I/O
DP[0-7] DPE DRTRY GBL GND
IN A RY
High Low Low Low --
I/O Output Input I/O --
HRESET INT L1_TSTCLK
1
A07 B15 D11 D12 B10
IM
C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12
Low Low -- -- Low Low -- -- High Low Low Low Low Low -- Low High Low High
Input Input Input Input Input Input -- -- Input Input Output Output Input Input Input Input Input I/O Output
L2_TSTCLK 1 LSSD_MODE 1 MCP NC (No-Connect) OVDD PLL_CFG[0-3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TC[0-1]
20
PR
C13 D03 J03 D01 A16 B14 C09 H14 C02 A14 A02, A03
B07, B08, C03, C06, C08, D05, D06, H04, J16 C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, P10 A08, B09, A09, D09
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Table 11. Pinout Listing for the 255 CBGA Package (Continued)
Signal Name TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ[0-2] TT[0-4] WT VDD2 VOLTDETGND3 Notes: C11 A11 A12 H13 C04 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D02 Pin Number Active -- High High Low Low I/O Input Input Output Input Input Input Input I/O Output I/O Output -- Output
IN A RY
High Low Low High High Low -- Low
F03
1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. 3. Internally tied to GND to indicate to the power supply that a low-voltage processor is present.
1.7 Package Descriptions
The following sections provide the package parameters and the mechanical dimensions for the PID7vEC603e. Note that the PID7v-EC603e is currently offered in two types of CQFP packages--the Motorola wire-bond CQFP and the ceramic ball grid array (CBGA) package.
1.7.1 Motorola Wire-Bond CQFP Package Description
The following sections provide the package parameters and mechanical dimensions for the Motorola wirebond CQFP package.
1.7.1.1 Package Parameters
The package parameters are as provided in the following list. The package type is 32 mm x 32 mm, 240-pin ceramic quad flat pack. Package outline Interconnects Pitch 32 mm x 32 mm 240 0.5 mm (20 mil)
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, L11
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1.7.1.2 Mechanical Dimensions of the Motorola Wire-Bond CQFP Package
Figure 11 shows the mechanical dimensions for the wire-bond CQFP package.
AB I R -H- 2
IN A RY
C G J A B C D E F G H J AA AB 1 3.75 0.18 3.10 0.13 0.45 0.25 2 1 2 R Wire Bonds
R AA
F
H
A
Notes: 1. BSC--Between Standard Centers. 2. All measurements in mm. Min. Max. 31.75
B
*Reduced pin count shown for clarity. 60
30.86 34.6 BSC
IM
4.15
0.5 BSC 0.30 3.90 0.175 0.55 -
PR
EL
1.80 REF 0.95 REF 6 7
Pin 240 Pin 1
0.15 REF Ceramic Body
D
E
Die
*Not to scale
Alloy 42 Leads
Figure 11. Mechanical Dimensions of the Motorola Wire-Bond CQFP Package
22
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
1.7.2 CBGA Package Description
The following sections provide the package parameters and mechanical dimensions for the Motorola CBGA packages.
1.7.2.1 Package Parameters
The package parameters are as provided in the following list. The package type is 21 mm x 21 mm, 255lead ceramic ball grid array (CBGA). Package outline Interconnects Pitch Package height Ball diameter Maximum heat sink force 21 mm x 21 mm 255 1.27 mm (50 mil)
Minimum: 2.45 mm Maximum: 3.00 mm 0.89 mm (35 mil) 10 lbs
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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IN A RY
23
1.7.2.2 Mechanical Dimensions of the CBGA Package
Figure 12 provides the mechanical dimensions and bottom surface nomenclature of the Motorola CBGA package.
2X
0.200
A1 CORNER
A
-E-
B
P
2X
0.200 -F- N
IM
IN A RY
-T- 0.150 T
DIM A B C D G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX INCHES MIN MAX
EL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
21.000 BSC 21.000 BSC 2.450 0.820 3.000 0.930
0.827 BSC 0.827 BSC 0.097 0.032 0.118 0.036
K
T R P N M L K J H G F E D C B A
PR
1.270 BSC 0.790 0.990
0.050 BSC 0.031 0.039
H C
H K N P
0.635 BSC 5.000 5.000 16.000 16.000
0.025 BSC 0.197 0.197 0.630 0.630
G
255X
K D
S S
0.300 0.150
TE T
S
F
S
Figure 12. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package
24
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the PID7v-EC603e.
1.8.1 PLL Configuration
The PID7v-EC603e PLL is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the PID7v-EC603e is shown in Table 12 for nominal frequencies.
CPU Frequency in MHz (VCO Frequency in MHz) PLL_CFG[0-3] Bus-toCore Multiplier 2x 2x 2.5x 3x 3.5x 4x Core-to VCO Multiplier 2x 4x 2x 2x Bus 25 MHz -- -- -- Bus 33.33 MHz Bus 40 MHz Bus 50 MHz Bus 60 MHz Bus 66.67 MHz 133 (266) -- 166 (333) 200 (400) 233 (466) Bus 75 MHz 150 (300) -- 187 (375) 225 (450)
0100 0101 0110 1000 1110 1010 0111 1011 1001 1101 0011 1111
IM
-- -- -- -- -- -- 125 (250) 137 (275) 150 (300) -- 133 (266) 150 (300) 166 (333) 183 (366) 200 (400)
EL
2x 2x
PR
4.5x
2x
IN A RY
-- -- -- -- -- 120 (240) 140 (280) 160 (320) 180 (360) 200 (400) 220 (440) 240 (480) PLL bypass Clock off -- -- -- -- 125 (250) 150 (300) 175 (350) 200 (400) 225 (450) -- -- -- -- -- -- --
Table 12. PLL Configuration
150 (300) 180 (360) 210 (420) 240 (480)
-- -- -- --
-- -- -- --
5x 5.5x 6x
2x 2x 2x
Notes: 1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not supported; see Section 1.4.2.1, "Clock AC Specifications," for valid SYSCLK and VCO frequencies. 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 3. In clock-off mode, no clocking occurs inside the PID7v-EC603e regardless of the SYSCLK input.
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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1.8.2 PLL Power Supply Filtering
The AVdd power signal is provided on the PID7v-EC603e to provide power to the clock generation phaselocked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to the AVdd pin to ensure it filters out as much noise as possible. The 0.1 F capacitor should be closest to the AVdd pin, followed by the 10 F capacitor, and finally the 10 resistor to Vdd. These traces should be kept short and direct.
10 10 F
Figure 13. PLL Power Supply Filter Circuit
1.8.3 Decoupling Recommendations
These capacitors should vary in value from 220 pF to 10 F to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values for the Vdd pins--220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the OVdd pins--0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors--100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum).
1.8.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the PID7vEC603e.
26
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Due to the PID7v-EC603e's dynamic power management feature, large address and data buses, and high operating frequencies, the PID7v-EC603e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PID7v-EC603e system, and the PID7v-EC603e itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd and OVdd pin of the PID7v-EC603e. It is also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance.
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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IN A RY
0.1 F GND
Vdd
AVdd
1.8.5 Pull-up Resistor Requirements
The PID7v-EC603e requires high-resistive (weak: 10 K) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PID7v-EC603e or other bus master. These signals are--TS, ABB, DBB, and ARTRY. In addition, the PID7v-EC603e has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 K-10 K) if they are used by the system. These signals are--APE, DPE, and CKSTP_OUT. During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the PID7v-EC603e must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the PID7v-EC603e. It is recommended that these signals be pulled up through weak (10 K) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are--A[0-31], AP[0-3], TT[0-4], TBST, and GBL. The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus.
1.8.6 Thermal Management Information
1.8.6.1 Motorola Wire-Bond CQFP Package
This section provides thermal management data for the PID7v-EC603e; this information is based on a typical desktop configuration using a 240 lead, 32 mm x 32 mm, Motorola wire-bond CQFP package. The heat sink used for this data is a pinfin configuration from Thermalloy, part number 2338.
1.8.6.1.1 Thermal Characteristics
The thermal characteristics for a wire-bond CQFP package are as follows: Thermal resistance (junction-to-case) = Rjc or jc = 2.2 C/Watt (junction-to-case)
1.8.6.1.2 Thermal Management Example
The following example is based on a typical desktop configuration using a Motorola wire-bond CQFP package. The heat sink used for this data is a pinfin heat sink #2338 attached to the wire-bond CQFP package with thermal grease. Figure 14 provides a thermal management example for the Motorola CQFP package.
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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This section provides thermal management data for the PID7v-EC603e. The information found in the first sub-sections is based on a typical desktop configuration using a 240 lead, 32 mm x 32 mm, Motorola wirebond CQFP package. The heat sink used for this data is a pinfin configuration from Thermalloy, part number 2338. The data found in the subsequent sub-sections concerns PID7v-EC603e's packaged in the 255-lead 21 mm multi-layer ceramic (MLC), ceramic BGA package. Data is shown for two cases, the exposed-die case (no heat sink) and using the Thermalloy 2338-pin fin heat sink.
IM
IN A RY
27
35 Junction-to-Ambient Thermal 30 Motorola Wire-Bond CQFP Resistance (C/watt) 25 20 15
5 0 0 1
2
IN A RY
3 4
10
With Heat Sink
5
Forced Convection (m/sec)
Figure 14. Motorola CQFP Thermal Management Example
The junction temperature can be calculated from the junction-to-ambient thermal resistance, as follows: Junction temperature: Tj = Ta + Rja * P or
Ta is the ambient temperature in the vicinity of the device Rja is the junction-to-ambient thermal resistance Rjc is the junction-to-case thermal resistance of the device Rcs is the case-to-heat sink thermal resistance of the interface material Rsa is the heat sink-to-ambient thermal resistance P is the power consumed by the device In this environment, it can be assumed that all the heat is consumed to the ambient through the heat sink, so the junction-to-ambient thermal resistance is the sum of the resistances from the junction to the case, from the case to the heat sink, and from the heat sink to the ambient. Note that verification of external thermal resistance and case temperature should be performed for each application. Thermal resistance can vary considerably due to many factors including degree of air turbulence. For a power consumption of 2.5 Watts in an ambient temperature of 40 C at 1 m/sec with the heat sink measured above, the junction temperature of the device would be as follows: Tj = Ta + Rja * P Tj = 40 C + (10 C/Watt * 2.5 Watts) = 65 C which is well within the reliability limits of the device.
28
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Where:
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Tj = Ta + (Rjc + Rcs + Rsa) * P
IM
Notes: 1. Junction-to-ambient thermal resistance is based on measurements on single-sided printed circuit boards per SEMI (Semiconductor Equipment and Materials International) G38-87 in natural convection. 2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G3088 with the exception that the cold plate temperature is used for the case temperature. The vendors who supply heat sinks are Aavid Engineering, IERC, Thermalloy, and Wakefield Engineering. Contact information for these vendors follows:
International Electronic Research Corporation (IERC) 135 W. Magnolia Blvd. Burbank, CA 91502 Aavid Engineering One Kool Path Laconic, NH 03247-0440 Wakefield Engineering 60 Audubon Rd. Wakefield, MA 01880
IM
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
1.8.6.2 Motorola CBGA Package
The data found in this section concerns PID7v-EC603e's packaged in the 255-lead 21 mm multi-layer ceramic (MLC), ceramic BGA package. Data is shown for two cases, the exposed-die case (no heat sink) and using the Thermalloy 2338-pin fin heat sink.
1.8.6.2.1 Thermal Characteristics
The internal thermal resistance for this package is negligible due to the exposed die design. A heat sink is attached directly to the silicon die surface only when external thermal enhancement is necessary. Additionally, the CBGA package offers an exceptional thermal connection to the card and power planes. Heat generated at the chip is consumed through the package, the heat sink (when used) and the card. The parallel heat flow paths result in the lowest overall thermal resistance as well as offer significantly better power consumption capability when a heat sink is not used.
1.8.6.2.2 Thermal Management Example
The following example is based on a typical desktop configuration using a solder-bump 21 mm CBGA package. The heat sink shown is the Thermalloy pinfin heat sink #2338 attached directly to the exposed die with a two-stage thermally conductive epoxy. The calculations are performed exactly as shown in the previous section.
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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IN A RY
818-842-7277 603-528-3400 617-245-5900
29
Thermalloy 2021 W. Valley View Lane P.O. Box 810839 Dallas, TX 75731
214-243-4321
Figure 17 shows typical thermal performance data for the 21 mm CBGA package mounted to a test card.
25
20
CBGA with Exposed Die
15
ja (C/W)
10
5
0 0 1
IM
2
IN A RY
3
Approach Air Velocity (m/sec)
CBGA with Thermalloy 2338B-Pin Fin Heat Sink
4
5
Temperature calculations are also performed identically to those in the previous section. For a power consumption of 2.5 Watts in an ambient of 40 C at 1.0 m/sec, the associated overall thermal resistance and junction temperature, found in Table 13, will result.
Table 13. Thermal Resistance and Junction Temperature
Configuration Exposed die (no heat sink) With 2338 heat sink ja (C/W) 18.4 5.3 Tj (C) 86 53
Vendors such as Aavid Engineering Inc., Thermalloy, and Wakefield Engineering can supply heat sinks with a wide range of thermal performance. Refer to Section 1.8.6.1.2, "Thermal Management Example," for contact information.
30
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Figure 15. CBGA Thermal Management Example
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Assumptions: 1. 2P card with 1 OZ Cu planes 2. 63 mm x 76 mm card 3. Air flow on both sides of card 4. Vertical orientation 5. 2-stage epoxy heat sink attach
1.9 Ordering Information
Figure 16 provides the Motorola part numbering nomenclature for the PID7v-EC603e. In addition to the processor frequency, the part numbering scheme also consists of a part modifier and application modifier. The part modifier indicates any enhancement(s) in the part from the original production design. The bus divider may specify special bus frequencies or application conditions. Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For available frequencies, contact your local Motorola sales office.
Product Code Part Identifier Part Modifier (P = Enhanced, Low-Voltage) Package (FE = Wire-Bond CQFP RX = CBGA w/o Lid)
IN A RY
MPE 603 P XX XXX X X
Revision Level (Contact Motorola Sales Office)
Application Modifier (L = Any Valid PLL Configuration) Processor Frequency
Figure 16. Motorola Part Number Key
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Appendix A General Handling Recommendations for the C4-CQFP
The following list provides a few guidelines for package handling: * * * * Handle the electrostatic discharge sensitive (ESD) package with care before, during, and after processing. Do not apply any load to exceed 3 Kg after assembly. Components should not be hot-dip tinned. The package encapsulation is an acrylated urethane. Use adequate ventilation (local exhaust) for all elevated temperature processes.
The package parameters are as follows: Heat sink adhesive IBM reference drawing Test socket Signal Power/ground Total AIEG-7655 99F4869 165 75 240
The environmental, operation, shipment, and storage requirements are as follows: * Make sure that the package is suitable for continuous operation under business office environments. -- Operating environment: 10 C to 40 C, 8% to 80% relative humidity -- Storage environment: 1 C to 60 C, up to 80% relative humidity -- Shipping environment: 40 C to 60 C, 5% to 100% relative humidity This component is qualified to meet JEDEC moisture Class 2. After expiration of shelf life, packages may be baked at 120 C (+10/-5 C) for 4 hours minimum and then be used or repackaged. Shelf life is as specified by JEDEC for moisture Class 2 components.
*
A.2 Card Assembly Recommendations
This section provides recommendations for card assembly process. Follow these guidelines for card assembly. * * * * This component is supported for aqueous, IR, convection reflow, and vapor phase card assembly processes. The temperature of packages should not exceed 220 C for longer than 5 minutes. The package entering a cleaning cycle must not be exposed to temperature greater than that occurring during solder reflow or hot air exposure. It is not recommended to re-attach a package that is removed after card assembly.
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A.1 Package Environmental, Operation, Shipment, and Storage Requirements
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Yamaichi QFP-PO 0.5-240P
IN A RY
During the card assembly process, no solvent can be used with the C4FP, and no more than 3 Kg of force must be applied normal to the top of the package prior to, during, or after card assembly. Other details of the card assembly process follow: Solder paste Solder stencil thickness Solder stencil aperature Placement tool Solder reflow Solder reflow profile Either water soluble (for example, Alpha 1208) or no clean 0.152 mm Width reduced to 0.03 mm from the board pad width Panasonic MPA3 or equivalent Infrared, convection, or vapor phase Infrared and/or convection * Average ramp-up--0.48 to 1.8 C/second * Time above 183 C--45 to 145 seconds * Minimum lead temperature--200 C * Maximum lead temperature--240 C * Maximum C4FP temperature--245 C Vapor phase * Preheat (board)--60 C to 150 C * Time above 183 C--60 to 145 seconds * Minimum lead temperature--200 C * Maximum C4FP temperature--220 C * Egress temperature--below 150 C
Clean after reflow
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Touch-up and repair C4FP removal C4FP replace
PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Hand solder
De-ionized (D.I.) water if water-soluble paste is used * Cleaner requirements--conveyorized, in-line * Minimum of four washing chambers --Pre-clean chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 70 C minimum, dwell time of 24 seconds minimum, water is not re-used, water flow rate of 30 liters/minute. --Wash chamber #1: top and bottom sprays, minimum top-side pressure of 48 psig, minimum bottom-side pressure of 44 psig, water temperature of 62.5 C (2.5 C), dwell time of 48 seconds minimum, water flow rate of 350 liters/minute. --Wash chamber #2: top and bottom sprays, minimum top-side pressure of 32 psig, minimum bottom-side pressure of 28 psig, water temperature of 72.5 C (2.5 C), dwell time of 48 seconds minimum, water flow rate of 325 liters/minute. --Final rinse chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 72.5 C minimum, dwell time of 24 seconds minimum, water flow rate of 30 liters/minute. * No cleaning required if "no clean solder paste" is used Water soluble (for example, Kester 450) or No Clean Flux Hot air rework
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PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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PID7v-EC603e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Mfax is a trademark of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. IBM is a trademark of International Business Machines Corporation. The PowerPC name is a registered trademark and the PowerPC logotype and PowerPC 603 are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK. Motorola Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 or 1-303-675-2140; World Wide Web Address: http://ldc.nmd.com/ JAPAN: Nippon Motorola Ltd SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan Tel.: 81-3-5487-8488 ASIA/PACIFC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong; Tel.: 852-26629298 MfaxTM: RMFAX0@email.sps.mot.com; TOUCHTONE 1-602-244-6609; US & Canada ONLY (800) 774-1848; World Wide Web Address: http://sps.motorola.com/mfax INTERNET: http://motorola.com/sps Technical Information: Motorola Inc. SPS Customer Support Center 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com. Document Comments: FAX (512) 891-2638, Attn: RISC Applications Engineering. World Wide Web Addresses: http://www.mot.com/SPS/PowerPC/ http://www.mot.com/SPS/RISC/netcomm/
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